1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a leak current reducing method, and particularly to a semiconductor integrated circuit having a circuit configuration effective in reducing a leak current consumed or used up by an SRAM memory circuit in a system LSI including the SRAM memory circuit, and a leak current reducing method.
This application is counterpart of Japanese patent application, Ser. No. 314287/2005, filed Oct. 28, 2005, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
With the proliferation of portable devices, there has recently been a demand for a reduction in power consumption of a semiconductor integrated circuit device more than ever before. Particularly, in a system LSI that combines various functional blocks within one chip, an SRAM realized by the same process as a logic system is configured as an important functional block which influences the performance of the system LSI. However, high integration of the SRAM mounted in the system LSI and an increase in capacity thereof have been advanced with process miniaturization. In order to achieve low power consumption of the system LSI, the reduction in power consumption of the SRAM increases in importance.
On the other hand, as the process miniaturization advances, a reduction in power supply voltage is being brought forward. When the power supply voltage is lowered, the operating speed of a MOS transistor becomes slow. As a countermeasure to avoid it, there is known a method for reducing the threshold voltage of the MOS transistor. However, a problem arises in that when the threshold voltage is lowered, a leak current at the time that the MOS transistor is off increases. The SRAM is made up of a memory cell array section for holding data, an external circuit and a peripheral circuit that performs swapping with the data, and has two operating states of an operating state and a standby state. In the standby state in which data of each memory cell is being held without performing write and read operations, only a leak current flows through the peripheral circuit and the memory cell, whereas in the operating state in which the write and read operations are performed, a charge/discharge current generated when load capacitance of each node in the SRAM is charged/discharged, and a through current generated upon switching of each individual MOS transistor constituting the SRAM flow as well as the leak current. As a proportion of current consumption in the SRAM, the charge/discharge current at or during operation has mainly been used. However, the power supply voltage is further reduced with advances in miniaturization from this time forward and the threshold voltage is also reduced. A rapid increase in leak current due to this yields a problem that the current consumption of the SRAM is greatly increased inclusive of during-operation as well as at-standby.
As a conventional method for reducing power consumption of a logic circuit, there has been disclosed in a patent document 1 (Japanese Laid-Open Patent Application No. Hei 6(1994)-53496), a method for mounting a substrate bias circuit and controlling a substrate potential of each MOS transistor by a substrate bias generating circuit at standby to make its threshold voltage higher than during operation, thereby reducing a leak current at standby.
As a method for bringing an SRAM circuit to low power consumption, there has been disclosed in a patent document 2 (Japanese Laid-Open Patent Application No. 2004-206745), a method for cutting off or interrupting a source potential of each drive NMOS transistor in an SRAM memory cell from a ground power supply by means of a switch at standby and thereafter setting the source potential to an intermediate voltage between the ground power supply and a power supply voltage by a source potential control circuit comprised of a diode and a resistor, thereby reducing a leak current of each memory cell at standby.
However, the above conventional configuration is the method for increasing the threshold voltage of each MOS transistor only at standby to thereby reduce the leak current. A problem arises in that the leak current during operation cannot be reduced. In the case of the method for controlling the substrate potential, a MOS semiconductor integrated circuit normally takes a vertical-stack configuration in which the drains of PMOS and NMOS transistors are connected to each other as in CMOS inverters. Therefore, it is not possible to desire a large reduction in leak current unless a substrate potential is applied to both NMOS and PMOS transistors to control both threshold voltages.
A typical SRAM memory cell comprises six MOS transistors. Described specifically, the SRAM memory cell is constituted of two load PMOS transistors, two drive NMOS transistors and two transfer NMOS transistors. Since the NMOS transistors are in majority in number, leak current components due to the NMOS transistors, which are assumed in the total leak current of the memory cell, increase. Therefore, in the case where a substrate bias control method is used, there is a need to fix a source potential Vsn for each NMOS transistor to a ground power supply and control a substrate potential Vbb for the purpose of a reduction in the leak current of the SRAM memory cell. However, in order to supply a potential different from the source potential to a substrate potential Vbb of a specific NMOS transistor in a semiconductor of a P-type substrate, a process for a triple well structure is necessary. It goes increase in process cost as compared with a generally-used signal well structure or twin well structure. As to a substrate potential Vpp for each PMOS transistor, there is no need to use the process for the triple well structure because a substrate for each PMOS transistor is normally connected to an NWELL and can be separated from the P-type semiconductor substrate to which the source potential is connected.
On the other hand, in the case of a method for controlling a source potential Vsn of each drive NMOS transistor, a substrate potential Vbb for the NMOS transistor is set as a ground power supply and a source potential Vsn is set higher than the ground power supply at standby. Thus, a reduction in leak current by a reverse bias effect of a gate-to-source voltage of each transfer NMOS transistor and voltage reduction effects of a drain-to-source voltage of each transfer NMOS transistor, a drain-to-source voltage of each drive NMOS transistor and a drain-to-source voltage of each load PMOS transistor is expected as well as a reduction in leak current of each of the drive and transfer NMOS transistors by a substrate bias effect. However, as compared with the reduction in leak of each of the drive and transfer NMOS transistors, the leak current flowing through the load PMOS transistors is low in reduction effect. Therefore, a problem arises in that a large reduction in leak current over the entire memory cell cannot be anticipated. Although there has been disclosed, as its countermeasure, a method for fabricating the load PMOS transistors by transistors each having a high threshold voltage in advance, there is a need to adopt a Multi-Vt process having plural threshold voltages for an internal logic circuit, and correspondingly process cost becomes high.
As a method for biasing a source potential of each drive NMOS transistor, there has been disclosed one in which a MOS resistor and a MOS diode are connected in parallel. However, a problem arises in that since the voltage value of a source bias is restricted by the threshold voltage of the MOS transistor, the source bias voltage value is susceptible to a process variation, a power supply voltage and temperatures and is apt to influence the effect of reducing a leak current. Since there is, in particular, a tendency that as miniaturization advances, a process variation in threshold voltage becomes large, the source bias voltage value exerts a greater influence on a leak reducing effect. In addition, a problem arises in that since the source bias voltage value is determined according to the balance between the threshold voltage of the MOS transistor and the resistance of the MOS transistor, and its value depends upon a leak current that flows through the SRAM memory cell at standby, it is difficult to set the source bias voltage value to an arbitrary value.
Further, the memory cell has the lowest operating voltage necessary to hold data at standby. While the SRAM operates in an operating voltage range higher than the lowest operating voltage and lower than the maximum power supply voltage of an SRAM power supply, the present operating voltage range becomes narrower as a reduction in power supply voltage advances with miniaturization. Therefore, it is important to generate a bias potential less subject to the process variation and high in accuracy upon ensuring stable retention of data.